In forwarded clock I/O links, one data channel is dedicated to forward the clock (e.g., differential signal) to a receiver. The forwarded clock is attenuated due to channel loss. The receiver recovers and deskews the clock so that it can sample received data in the middle of the eye.
FIG. 1 illustrates an example receiver 100 used to recover a forwarded clock in order to accurately sample data. The receiver 100 includes a clock recovery unit 110, a clock buffer 140, and first and second data receivers 150, 160. The clock recovery unit 110 includes a pre-amplifier 115, a delay lock loop (DLL) 120, a multiplexer 130, and an interpolator 135. The data receivers 150, 160 include amplifiers 152, 162 and latches 154, 164 respectively.
The forwarded clock signal is received and amplified by the pre-amplifier 115 which provides the forwarded clock to the DLL 120. The DLL 120 generates N clock phases based on the forwarded clock. The N clock phases are provided to the multiplexer 130 that may select two clock phases (e.g., 0 to 180 degrees CLK, 0 to -180 degrees for CLKBAR) out of N phases generated by N-stage DLL 120. The interpolator 135 may interpolate the two selected clock phases so a clock phase between 0-360 degrees may be generated with high resolution (e.g., within 1°). The recovered clock may be provided to the latches 154, 164 via the clock buffer 140. The clock buffer 140 is used to absorb the capacitive loading of the receiver latches 154, 164. Each latch 152, 154 may receive a different leg of the recovered clock signal (e.g., CLK to 154, CLKBAR to 164). Data is received by the amplifiers 152, 162 and the data is clocked into the latches 154, 164 based on the recovered clock provided.
The components of the clock recovery unit 110 (the pre-amplifier 115, the DLL 120, the multiplexer 130 and the interpolator 135) may be delay sensitive to supply noise and accordingly supply noise jitter may be induced in the forwarded clock. The jitter induced in the forwarded clock may be amplified due to bandwidth limitation of clock deskewing path. Due to large number of delay cells used to implement the clock recovery unit 110, the receiver 100 may consume significant power.